Power Electronics Design & Analysis for EV Applications
Analyze and optimize power electronics topologies for EV drivetrains and charging systems
What You Can Do
You can evaluate converter topologies (buck, boost, bidirectional, LLC architectures), calculate component losses and thermal performance across operating conditions, perform derating analysis for MOSFETs/IGBTs/diodes, identify failure modes and stress points, and generate efficiency maps and thermal specifications. This skill accelerates design validation and helps you compare trade-offs between cost, efficiency, size, and thermal performance before detailed simulation.
Features
evaluate buck, boost, bidirectional, and LLC converter architectures with SiC vs IGBT trade-off analysis
calculate junction temperatures, thermal resistance networks, and heatsink requirements for power devices
compute conduction and switching losses across load and voltage operating ranges
validate semiconductor selection against datasheet limits and operating stress
identify FMEA points, stress concentrations, and reliability concerns in proposed designs
generate efficiency curves across multiple operating conditions for performance validation
compare cost, efficiency, size, and thermal performance alternatives
create detailed design review documentation and thermal/electrical specifications for development teams
Example Output
Example 1: Topology Selection for 11 kW Onboard Charger
- Evaluated three topologies: Interleaved Boost + LLC, Totem-Pole PFC, and Bridgeless Boost
- Recommended Totem-Pole with SiC MOSFETs: 96.2% efficiency at rated power, 15°C lower junction temperature vs IGBT variant
- Identified critical stress point: High dV/dt across output capacitors; recommended film capacitors with 1.5× voltage derating
Example 2: Thermal Analysis for DC-DC Converter (400V to 12V)
- Calculated total losses: 18W conduction + 12W switching at full load
- Thermal path: Tj = 85°C with proposed aluminum heatsink (0.5 K/W) in natural convection
- Recommended thermal interface material: 0.5 mm silicone pad (3 W/mK) to reduce interface resistance
Example 3: Failure Mode Assessment
- Identified gate-to-source voltage stress during switching transients; recommended 10Ω gate resistance for snubbing
- Derating analysis: MOSFETs operating at 78% of rated Vds; adequate margin for 150°C ambient condition
What's Included
- SKILL.md instruction file with detailed skill methodology:
- Topology Evaluation Framework: comparison matrix template for converter architectures with efficiency/cost/thermal trade-offs
- Thermal Analysis Worksheet: loss calculation templates, thermal resistance network model, and junction temperature calculator
- Component Derating Checklist: semiconductor stress validation against datasheet parameters
- Failure Mode Analysis Template: FMEA-style assessment for identifying critical failure points and mitigation strategies
- Design Review Documentation Template: structured format for presenting analysis results to engineering teams
Who It's For
- Power electronics design engineers working on EV drivetrain converters and onboard chargers
- Automotive electrical engineers optimizing DC-DC converters and power distribution systems
- Hardware validation engineers conducting early-stage thermal and reliability assessments
- EV systems engineers comparing topology options and design trade-offs during concept phase
- Technical leads preparing design reviews and component selection justifications
Best For
- Evaluating converter topology options (buck, boost, bidirectional, LLC) for new EV applications
- Performing thermal and efficiency calculations for power device selection validation
- Identifying failure modes, stress points, and derating requirements in proposed designs
- Generating efficiency maps and thermal specifications for heatsink development
- Creating design trade-off comparisons (cost vs efficiency vs size vs thermal performance)
- Validating component selections against datasheet limits and operating conditions
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